Microprocessor controlled tuning systems are being widely used in television receivers. One approach to such tuning systems is to use a microprocessor to control a PLL that corrects for drift in the local oscillator phase thereby insuring that the local oscillator is always precisely in phase with a fixed frequency crystal oscillator. A specific example of an electronic, mircroprocessor controlled television tuning system is disclosed in U.S. Pat. No. 4,280,140 issued to Peter C. Skerlos. In this system, AFC discriminator information is provided to the microprocessor for the generation of digital outputs for controlling stepwise tuning adjustments. This information is generated by a pair of window comparators, edge/direction comparator, and a vertical sync detector. When a channel is selected, the tuning system first synthesizes the correct frequency for that channel. Then the microprocessor first looks at the output of the edge/direction comparator to determine the direction of tuning. Once the proper tuning direction is determined by the edge/direction comparator, the microprocessor then steps the AFC tuning voltage in predetermined increments until the limit of the number of allowed steps for that particular channel is reached. When this limit is reached and no carrier is found, tuning is switched and the voltage stepping procedure is initiated again. For a detected carrier to be valid, the output of the window comparators should be high and the vertical sync detector should produce a train of 60 Hz pulses, indicating the presence of vertical sync information. Although one would expect the Skerlos system to work well, in the highly competitive television market the cost of implementing such a system is objectionable.
An alternative tuning system is disclosed in the above-referenced application Ser. No. 06/501,685 filed by Terrence E. Rogers uses a single detector whose threshold is controlled by the microprocessor for detecting the arrival at the proper frequency. More specifically, the mircroprocessor sends frequency data to the PLL. The PLL also receives a sample of the voltage controlled oscillator (VCO) located in the tuner and compares it with a crystal standard by dividing the VCO sample according to the frequency data and applying it to a phase detector whose other input is connected to a divided down crystal oscillator signal. The phase detector produces output pulses that vary in width and polarity as a function of whether the VCO signal is above or below the proper frequency and phase required by the frequency data. A loop filter converts the pulses into a varying d.c. voltage which in turn is used to control the VCO. A portion of the i.f. amplifier is arranged so that it can detect errors in the desired i.f. This automatic frequency control (AFC) detector is connected to an AFC comparator whose output is connected to the microprocessor. The output of the AFC comparator is a logic "1" if the carrier frequency is higher than the input data value and a logic "0" if the carrier frequency is lower than the input data value. The microprocessor has an offset control so that the exact value of voltage at which the AFC comparator switches from a logic "1" to a logic "0" can be controlled by the microprocessor.